module top(output N, output E, output W, output S, output G, input hwclock, output pmod_1, input pmod_2, output ftdi_tx);

    reg [31:0] counter = 32'b0;

    assign G = counter[21];
    assign N = counter[22];


    wire busy;
    
    serial foo (hwclock, "q", 0, 1, ftdi_tx, busy);

    always @ (posedge hwclock) begin
        counter <= counter + 1;
    end

endmodule


module serial(input hwclock, input [7:0] char, input reset, input send, output reg out, output busy);

    reg [12:0] counter;
    reg [7:0] char1;

    assign busy = (state == IDLE) ? 1'b1 : 1'b0;

    localparam IDLE = 4'd0, START = 4'd1;
    localparam BIT0 = 4'd2, BIT1 = 4'd3, BIT2 = 4'd4, BIT3 = 4'd5, BIT4 = 4'd6,
               BIT5 = 4'd7, BIT6 = 4'd8, BIT7 = 4'd9, STOP = 4'd10;
    localparam SPACE = 1'b0;
    localparam MARK = 1'b1;

    reg [3:0] state = IDLE;

    always @ (posedge hwclock) begin
        if (reset) begin
            state <= IDLE;
            counter <= 0;
        end else if (state == IDLE) begin
            if (send == 1) begin
                state <= START;
                counter <= 0;
                char1 <= char;
            end
        end else begin
            // 12_000_000 / 9600 = 1250
            if (counter < 1250) begin
                counter <= counter + 1;
            end else begin
                counter <= 0;
                if (state != STOP) begin
                    state <= state + 1'b1;
                end else begin
                    state <= IDLE;
                end
            end
        end
    end

    always @ (*) begin
        case (state)
            IDLE: out = MARK; // Stop bit is also IDLE
            START: out = SPACE;
            BIT0: out = char1[0];
            BIT1: out = char1[1];
            BIT2: out = char1[2];
            BIT3: out = char1[3];
            BIT4: out = char1[4];
            BIT5: out = char1[5];
            BIT6: out = char1[6];
            BIT7: out = char1[7];
            default: out = MARK;
        endcase
    end
endmodule